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CoreFFT Fast Fourier Transform
I/O Signal Description
Figure 4 shows the CoreFFT module pinout.
FFT
d_im
d_re
d_valid
start
read_y
nreset
clk
load
pong
y_im
y_re
y_valid
y_rdy
Figure 4 ? CoreFFT I/O Signals
The CoreFFT module I/O signal functionality is listed in Table 6 . It is assumed that the module has been configured to
compute an N-point FFT/IFFT.
Table 6 ? I/O Signal Description
Signal Name Direction Description
clk
nreset
d_im[ b – 1:0]
d_re[ b – 1:0]
d_valid
load
start
y_rdy
y_im[ b – 1:0]
y_re[ b – 1:0]
8
Input
Input
Input
Input
Input
Output
Input
Output
Output
Output
System clock. Active rising edge.
System asynchronous reset. Active low.
Input imaginary data bus. The imaginary part of the input complex data should be placed on this bus. Bit
b – 1 is the MSB. Data are assumed to be presented in two’s-complement format. The imaginary and real
parts should be supplied simultaneously.
Input real data bus. The real part of the input complex data should be placed on this bus. Bit b – 1 is the
MSB. Data are assumed to be presented in two’s-complement format. The imaginary and real parts
should be supplied simultaneously.
Input complex word valid. Active high. The bit accompanies valid input samples coming to input busses
d_im and d_re . At any system clock interval where d_valid is active, input busses d_im and d_re are
considered to present another input complex sample.
The FFT module input buffer accepts data. Active high. The signal is active when the input buffer (either
of two banks) is ready to accept data. The signal stays active until the buffer is full.
FFT start signal. Active high. start is asserted to begin the transform processing or to return the module to
the initial ready state.
FFT results ready. Active high. The signal goes active when the FFT results are ready for the host to read. It
stays HIGH during host read.
Output imaginary data bus. The imaginary part of the output complex data appears on this bus. Bit b – 1
is the MSB. Data are presented in two’s-complement format. The imaginary and real parts appear
simultaneously.
Output real data bus. The real part of the output complex data appears on this bus. Bit b – 1 is the MSB.
Data are presented in two’s-complement format. The imaginary and real parts appear simultaneously.
v4.0
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